The present invention relates to an integrated circuit that includes programmable logic such as a field programmable gate array, dedicated logic such as an ASIC type device, and an interface for communication between the programmable and dedicated devices.
The semiconductor industry is driven with a desire to provide higher levels of integration. With higher levels of integration, silicon space and cost are reduced while performance and reliability are increased. Unfortunately, higher levels of integration lead to greater specificity. For example, application specific integrated circuits (ASICs) are highly specific devices that often serve the needs of only one customer.
Programmable logic devices, such as field programmable gate arrays (FPGAs) are versatile integrated circuit chips, which have internal circuitry logic with user selected connections that a user can configure to realize user-specific functions. While programmable logic is versatile, there are significant design challenges in size, routing, pin-out stability when mapping large complex functions onto a silicon platform containing programmable logic.
While programmable logic devices may be linked with separate dedicated devices, there are associated on/off chip delays, large board area, and high cost. Further, while programming a programmable logic to perform the desired function is possible, this is an expensive proposition and the resulting performance is often not acceptable.
Consequently, what is needed is a single integrated device that combines the flexibility of programmable logic with the performance and reliability of a dedicated device.
Programmable logic, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that uses the technology of the programmable logic provides a convenient on-chip configuration of or parameter setting for the dedicated device. In one embodiment, the platform for the programmable logic is one half of an existing programmable logic device, which advantageously eliminates the need to engineer the programmable logic. The dedicated device can implement a complex but often required functions such as a bus interface for an industry standard bus, while the programmable circuit permits the user to implement custom functionality. Placing both the dedicated device and the programmable logic on the same chip allows a high throughput between the circuits but does not require a larger number of I/O pins because the communication is internal to the integrated circuit chip.
The programmable logic can include a clock network that receives clock signals from input/output terminals as well as from a clock network in the dedicated device. Accordingly, the programmable logic can operate at a frequency independent of the dedicated circuit. Input/output clock terminals for the programmable logic are generally on a side of the chip closest to the programmable logic, while the input/output clock terminals for the dedicated device are on the opposite side of the chip closest to the dedicated device. The clock network distributes the clock signals to both the programmable logic and the dedicated device.
The interface between the dedicated device and programmable logic includes a number of conductors having buffers and testing circuitry. The testing circuitry includes a PMOS test transistor and an NMOS test transistor which have their gates coupled to the output terminals of the buffers. The PMOS test transistor is coupled between a voltage source and an output terminal, while the NMOS test transistor is coupled between a ground source and a different output terminal. The output terminal of the PMOS test transistor is coupled to the output terminal of an inverter. During test mode, the inverter is tied to a voltage source. The PMOS test transistor is larger than the NMOS transistor in the inverter. Thus, when the PMOS test transistor is off the inverter drives the output terminal low, but when the PMOS test transistor is on the PMOS test transistor drives the output terminal high. The output terminal of the NMOS test transistor is coupled to the output terminal of another inverter, which is tied to a ground source during testing. The NMOS test transistor is larger than the PMOS transistor in the inverter. The testing circuitry advantageously permits testing of the buffers without programming the antifuses coupled to the conductors.
In accordance with another embodiment of the present invention, the input/output terminals around the periphery and in the interface between the programmable logic and dedicated device are tested using JTAG registers. The path of the test signal through the JTAG registers is selectable to pass around the periphery of both the programmable logic and the dedicated device or through the interface and around the periphery of the dedicated device.